Modern integrated circuits are typically constructed in a thin layer in a semiconducting layer on a substrate wafer such as silicon. This essentially two-dimensional structure limits both the size of the integrated circuit and the speed at which the circuit operates. The distance between the farthest separated components that must communicate with one another on the chip determines the speed at which an integrated circuit operates. For any given number of components, the path lengths will, in general, be significantly reduced if the circuit can be laid out as a three dimensional structure consisting of a number of vertically-stacked layers of circuitry, provided the vertical distance between the layers is much smaller than the width of the chips that make up the individual layers.
The circuitry that can be economically constructed on any type of wafer is limited. For example, the fabrication processes utilized for constructing CCD optical sensors do not lend themselves to constructing CMOS logic circuits. Hence, an optical sensor having a CCD array and the corresponding logic circuits must be broken into two substrates that are connected electrically after the circuit elements on each substrate have been fabricated. Such hybrid circuits are limited in the number of inter-substrate connections that can be utilized.
One promising scheme for providing such stacked structures utilizes a method for stacking and bonding entire wafers. In this method, integrated circuits are fabricated on conventional wafers. The circuitry on the front surface of each wafer is covered with an insulating layer having metallic pads that make contact with the underlying circuitry and act as electrical connection points between the two wafers. The front surfaces of the wafers are then placed in contact with one another and bonded via thermal compression bonding. If more than two wafers are to be connected, one of the wafers is then thinned to a thickness of a few microns by etching or mechanically grinding the back surface of that wafer. Once the wafer has been thinned, a new set of pads is constructed on the backside of the thinned wafer. Some of these backside pads are connected to the circuitry on the front side of the wafer through vias that connect the front and back sides of the thinned wafer. These backside pads provide the connection points for adding yet another wafer to the stack. The process is then repeated until the desired number of layers has been bonded to form the three-dimensional stack. The three-dimensional stack is then cut into three-dimensional chips and packaged.
The metallic pads that are used to make circuit connections between the wafers typically have insufficient area to bond the wafers together with sufficient force to withstand the thermal cycling inherent in the fabrication process. Even in circuits that have thousands of circuit connection pads, the fraction of the wafer area that is covered by these bonding points is still a small fraction of the total wafer area. Hence, additional large areas of metal are deposited on each wafer in the areas between the circuit connection pads to provide additional bonds. All of these pads are typically made from the same metal used in the thermal compression bonding of the connection pads, and are bonded during the same thermal compression bonding step.
The bonding process requires that the metal surface on the two wafer surfaces be uniformly flat over the entire 8 to 12 inch wafer to a precision of a fraction of a micron. If the surface of a bonding pad is not flat, the actual area of metal that will be bonded will be only a small fraction of the pad area, and the bond will be prone to failure when the wafer stack is subjected to thermal stresses during subsequent processing.
In general, prior art bonding procedures utilize a chemical-mechanical polishing (CMP) procedure to planarize the surface of the metallic bonding pads prior to the thermal compression bonding step. CMP planarization is typically carried out in an apparatus having planar polishing pads that are moved over the surface of the substrate in the presence of a solution that includes abrasive particles.
Metal CMP processes are now a well-established semiconductor process for manufacturing logic and memory devices. Most of the current metal thin films (W, Cu, Al, Ir, Pt etc) are deposited by PVD, CVD and ECP in order to fill patterns such as trenches, contacts, and vias. For example, a Cu metal thin film is typically deposited by first depositing a PVD seed Cu layer followed by electro-chemically plated (ECP) Cu or chemical vapor deposited (CVD) Cu. After depositing the metal, the surface of the wafer has hills and valleys that can interfere with subsequent deposition steps; hence, the surface is planarized to remove these features and provide a flat surface for subsequent deposition steps.
While CMP has been used successfully for the planarization of wafers having a single surface composition such as SiO2 or Cu, problems are encountered when the procedure is applied to a surface having features that are eroded at different rates by the polishing pads and polishing solution. For example, if large copper pads that are inset in SiO2 are used for the additional bonding pads, the copper in the center of the pad is eroded at a faster rate than the copper on the sides of the pad that are set in SiO2, because the SiO2 erodes at a slower rate than the copper. This differential erosion leads to a pad that is dish-shaped. The bonding area of such a pad will be limited to a ring around the outer edge of the pad, and hence, only a small fraction of the pad area will bond to the corresponding pad on the adjacent wafer. The resulting bond is prone to failure because of its limited bond area.
In addition to failure of the metal-metal bond on the pads, the wafer-wafer bond can fail because the metal bonding pad is pulled off of the underlying SiO2 surface when the bonded wafers are subjected to thermal stress. Wafer-wafer bond failures resulting from the detachment of the metal pads are also observed when prior art stacking procedures are followed.